Further Logic Analysis, plus SSD Destruction

It’s been a relatively fruitful month with this project. After struggling to work out why I was getting some weird signals being measured by my logic analyser (word to the wise: don’t forget to connect GND), I managed to get some relatively meaningful waveforms, meaning I could properly start to write a sigrok decoder.

Writing a decoder was a slight challenge as I had never touched Python before, but I was able to get something working in about 24 hours!

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The SSD Port and (finally) Some Logic Analysis

I now have everything I need to get started on revealing the secrets of the Psion SSD Port. So, here’s what I’ve been up to this morning.

Rather than pull apart my “production” 3c, I’ve decided to get to work on a slightly broken 3a. I don’t like the idea of doing something dumb thanks to my inexperience and blowing up my 3c. The 3a’s battery compartment is in a pretty bad way, but it powers on quite happily with a Series 3 external PSU. So, I pulled it apart and got to work.

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Logic Analysers, CPLDs and Dunning-Kruger | Details

It’s been a few weeks since my last update on this project. This is partly because I’ve been waiting for a couple of bits to arrive, specifically a logic analyser based on the CY7C68013A and an Altera MAX II EPM240 board. But to be honest, the delay is mostly because I’ve realised how much I need to learn. I mean, I kind of knew that I needed to learn a lot, but I didn’t actually realise how little I already knew. Trust me, folks, Dunning-Kruger is very real and has smacked me in the face with its pointy inverted curve. Again.

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The Noob Looks At FPGAs and CPLDs

When I started thinking about this project, I knew there was going to be quite a steep learning curve. Picking up JavaScript after a long absence, trying to wrap my head around C after trying (and failing) to do so about 20 years ago, learning more about electronics than just holding a soldering iron the right way around.

What I wasn’t expecting to learn was how to design a microchip.

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SSDs, the ASIC4 and the SIBO Serial Protocol

Psion were a clever bunch, but like many companies in the early 90s they didn’t really do standards. Although the 3c and 3mx had a proper RS-232 serial port (albeit using a very odd connector), all of the earlier models used a proprietary protocol called the SIBO Serial Protocol. All Series 3 models used SSDs that also communicated using this proprietary protocol.

A significant part of developing this equipment involves working out how to emulate an SSD or Psion peripheral. Luckily, while trawling the Internet for Psion PDFs I found the Psion SIBO Hardware Development Kit. This book gives a breakdown of how to create equipment for the Psion Series 3 and 3a, including the controller chips needed, the Psion serial protocol, and how to write drivers for the Series 3 and 3a.

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