Logic Analysers, CPLDs and Dunning-Kruger | Details

Sat, 13 Oct 2018 00:00:00 0000

It’s been a few weeks since my last update on this project. This is partly because I’ve been waiting for a couple of bits to arrive, specifically a logic analyser based on the CY7C68013A and an Altera MAX II EPM240 board. But to be honest, the delay is mostly because I’ve realised how much I need to learn. I mean, I kind of knew that I needed to learn a lot, but I didn’t actually realise how little I already knew. Trust me, folks, Dunning-Kruger is very real and has smacked me in the face with its pointy inverted curve. Again.

So, I’ve been learning. One of my first ports of call was Udemy. I’ve got a collection of courses building in my Wishlist, including ones on C, ARM assembly, VHDL and even one on using Blender for 3D printing. But I’ve started the ball rolling with a Crash Course on Electronics and PCB Design by the fantastic André LaMothe. So far the course has been recapping things I learned back in school 25 years ago in Physics and Design Technology lessons, so much of it is familiar to me. But I’m missing a lot of practical knowledge, not to mention having forgotten all the important formulae for working with electricity and electronics. And I know that in a few lessons time I’ll heading into completely new territory. This course is almost 90 hours long and I got it on offer for £10.99. It’s worth much more than that.

I’ve also been trawling YouTube for related videos. I’ve watched a lot of videos on hacking retro hardware, including a batch of videos with someone repairing a lot of Sinclair ZX Spectrums. I’m yet to find any videos of people modifying any Psion kit (he says, trying to drag the narrative back to the project in hand), but maybe I haven’t been looking hard enough. Of course, I’ve watched a lot of the Ben Heck Show, but I guess that’s pretty obligatory.

Otherwise, I’ve been scouring the internet for long-abandoned websites dedicated to Psion kit. It’s been slow going, but I’ve found one or two gems. Of course, if you have any information then please let me know!

Now that the logic analyser and CPLD have arrived and I’ve installed a lot of development software, my next task for this project is to build a breakout board so that I can look at the traffic between the Series 3c and my Psion Flash SSD.

I think I’m going to need to get a stock of old Psion SSDs, both working and dead, because I don’t want to fry my only SSD (which has actual written work on it). If anyone knows anyone with a pile of them going spare, do get in touch. Actually, I’ll take on any old Psion kit, alive or dead. I’m pretty sure I’m going to damage some kit somewhere along the line, especially given my rookie status. Having spares would be invaluable.

Tell any potential donors that it’s for the good of worldwide technological development.

Right, back to the course. Only another 84 hours to go…

The Noob Looks At FPGAs and CPLDs

Wed, 19 Sep 2018 00:00:00 0000

When I started thinking about this project, I knew there was going to be quite a steep learning curve. Picking up JavaScript after a long absence, trying to wrap my head around C after trying (and failing) to do so about 20 years ago, learning more about electronics than just holding a soldering iron the right way around.

What I wasn’t expecting to learn was how to design a microchip.

As I said in my last log, I am worried that a regular ARM microcontroller won’t be fast enough to handle the 3.84 MHz clock speed of the data coming from the Psion Series 3c. It’s something I hadn’t considered at the beginning, as I assumed that processors had come on enough in the 27 years since the original Series 3 was released that they would be able to handle the speed.

Fortunately, a few very kind people have already sent me messages with ideas on how to tackle this.

On comp.sys.psion.misc (via Google Groups), Theo gave me some food for thought:

The protocol is rather interesting. I think doing it in a CPLD (basic FPGA) would probably be most flexible, but I can understand that’s a place you don’t want to go. Also, you need to a device with 5V capability, which is quite rare nowadays.

It sounds like the tricky bit is dealing with the up-to-5MHz input signal. I wonder whether you could take a couple of 12-bit shift registers. One is an input, which latches data coming out of the ASIC. The other is an output, which you enable to send data to the ASIC. With a little bit of control logic to handle synchronisation and latching, it essentially reduces your 5MHz one-bit problem to a 400kHz parallel-word problem, which is a lot easier to deal with in software.

Depending what you feel comfortable with, you could have a couple of shift register chips in TTL logic, and then wrap up the control logic in another programmable logic device (PAL, GAL, CPLD, whatever you prefer). Or maybe it’s simple enough to do in a few TTL logic gates.

Shift registers didn’t even cross my mind when I started, but using them makes sense. What I need to work out is how to control the data going back to the Psion. I think I would need to monitor the incoming IO, checking the first three bits sent from the 3c for a data request command, then get the output shift register to send data back. (Assuming I have understood the way the SIBO Serial Protocol works, that is.)

The thing is, I hadn’t heard of FPGAs before a week ago and the first time I’d come across a CPLD was in Theo’s message. So, as I’m sure you can see, using programmable logic chips is a completely different paradigm for me. Using them adds more questions to a project that already seems very complicated to me. For example, will I be able to get enough current from the 3c to be able to power both a CPLD or FPGA and a microprocessor? How do I get them to talk to each other? Not only that, how do I go about learning VHDL?

First, though, I need to really understand what’s going on between an SSD and the 3c. At Theo’s suggestion, I have already ordered a CY7C68013A-based logic analyser (under £4 on eBay, shipped from China) so that I can look at the data going back and forth. In an ideal world I would be able to tell which end of the wire is sending data at any given time. I do like Theo’s suggestion on this:

For instance, gimp the power supply so the SSD voltage is slightly lower than the other, or something like that?

That might be the easiest option. I need to build a “break-out” cable anyway, so that I can use an SSD outside the 3c. Perhaps I can connect up a separate 5v supply on a slightly different voltage? Of course, this could be an ideal project for me to get going with programmable logic.

So, I’m currently worrying about which FPGA or CPLD development board to buy. Do I go with Xilinx or Altera? Is one manufacturer’s software better than the other’s? Do I buy one with an in-built JTAG programmer? What size is suitable for this? How much money is this all going to cost me?

Like I said, I wasn’t expecting to have to think about these things when I started. But I’m not going to lie, there’s part of me that’s a little excited. The kid who wanted to build his own computer is finally getting his wish.

Cpld on The Last Psion

Logic Analysers, CPLDs and Dunning-Kruger | Details

The Noob Looks At FPGAs and CPLDs