Posts for: #Ssd

Psion SSD Drive, anyone?

Raspberry Pi Pico on a breadboard, with wires connecting to a SIBO SSD

I wanted to put out an update about my various Psion projects. I’ve been away for a while, thanks to some mental health issues culminating in a career change. It’s only in the last week or so that I’ve felt able to look at projects like this again; projects I enjoy but for which I just didn’t have the mental energy.

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The Siena SSD Drive

A Psion Series 3mx next to a Siena SSD Drive

It’s been an interesting morning. I’ve been digging around in the internals of the Siena SSD drive and made some discoveries.

The Siena SSD drive was released so that the diminutive Siena could still read SSDs. I bought one of these on eBay a week ago because I wanted to answer a question: “How did Psion get the SIBO Serial Protocol to work over RS-232?”

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A long overdue update - ASIC replication and VHDL

Diagram of ASIC4

It’s been far too long since my last update on this project. It’s the usual excuse (“I’m sorry, but life just got in the way, blah blah blah.”) and to those of you who are taking an interest in my little WiFi Pack project, not to mention the rest of the efforts of the Last Psion project, I can only apologise. For now, here’s a brief update on what I’ve been up to.

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Updates

I can’t believe it’s been two months since I last posted here. Much has happened on this project and, although I don’t have time to write in detail about these things now, I wanted to give you a brief overview. Warning: Expect Exclamation Marks.

A Co-Conspirator Has Been Found!

Karl happened to be working on a Psion SSD project at the same time as me and asked me if I wanted to collaborate. I was apprehensive at first - us techies can be quite possessive of our projects at times - but it’s been working brilliantly. We’re approaching the SSD challenge from two different angles, which has actually helped in analysing the SIBO platform. So if I refer to “we” rather than “I”, you know I’m talking about Karl and me.

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Further Logic Analysis, plus SSD Destruction

It’s been a relatively fruitful month with this project. After struggling to work out why I was getting some weird signals being measured by my logic analyser (word to the wise: don’t forget to connect GND), I managed to get some relatively meaningful waveforms, meaning I could properly start to write a sigrok decoder.

Writing a decoder was a slight challenge as I had never touched Python before, but I was able to get something working in about 24 hours!

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